PIC18LF25K50 Configuration Bits

First step to start developing with this microcontroller is to know how to configure the basic hardware to let it run.

Following I'm copying the Configuration Bits Microchip documentation, you can find it executing next command

  mcc18.exe -p=18LF25K50 --help-config

Obtained data is:

Configuration settings available for processor PIC18LF25K50

  PLL Selection:
    PLLSEL = PLL4X      4x clock multiplier
    PLLSEL = PLL3X      3x clock multiplier

  PLL Enable Configuration bit:
    CFGPLLEN = OFF      PLL Disabled (firmware controlled)
    CFGPLLEN = ON       PLL Enabled

  CPU System Clock Postscaler:
    CPUDIV = NOCLKDIV   CPU uses system clock (no divide)
    CPUDIV = CLKDIV2    CPU uses system clock divided by 2
    CPUDIV = CLKDIV3    CPU uses system clock divided by 3
    CPUDIV = CLKDIV6    CPU uses system clock divided by 6

  Low Speed USB mode with 48 MHz system clock:
    LS48MHZ = SYS24X4   System clock at 24 MHz, USB clock divider is set to 4
    LS48MHZ = SYS48X8   System clock at 48 MHz, USB clock divider is set to 8

  Oscillator Selection:
    FOSC = LP           LP oscillator
    FOSC = XT           XT oscillator
    FOSC = HSH          HS oscillator, high power 16MHz to 25MHz
    FOSC = HSM          HS oscillator, medium power 4MHz to 16MHz
    FOSC = ECHCLKO      EC oscillator, high power 16MHz to 48MHz, clock output
                        on OSC2
    FOSC = ECHIO        EC oscillator, high power 16MHz to 48MHz
    FOSC = RCCLKO       External RC oscillator, clock output on OSC2
    FOSC = RCIO         External RC oscillator
    FOSC = INTOSCIO     Internal oscillator
    FOSC = INTOSCCLKO   Internal oscillator, clock output on OSC2
    FOSC = ECMCLKO      EC oscillator, medium power 4MHz to 16MHz, clock
                        output on OSC2
    FOSC = ECMIO        EC oscillator, medium power 4MHz to 16MHz
    FOSC = ECLCLKO      EC oscillator, low power <4MHz, clock output on OSC2
    FOSC = ECLIO        EC oscillator, low power <4MHz

  Primary Oscillator Shutdown:
    PCLKEN = OFF        Primary oscillator shutdown firmware controlled
    PCLKEN = ON         Primary oscillator enabled

  Fail-Safe Clock Monitor:
    FCMEN = OFF         Fail-Safe Clock Monitor disabled
    FCMEN = ON          Fail-Safe Clock Monitor enabled

  Internal/External Oscillator Switchover:
    IESO = OFF          Oscillator Switchover mode disabled
    IESO = ON           Oscillator Switchover mode enabled

  Power-up Timer Enable:
    nPWRTEN = ON        Power up timer enabled
    nPWRTEN = OFF       Power up timer disabled

  Brown-out Reset Enable:
    BOREN = OFF         BOR disabled in hardware (SBOREN is ignored)
    BOREN = ON          BOR controlled by firmware (SBOREN is enabled)
    BOREN = NOSLP       BOR enabled in hardware, disabled in Sleep mode
                        (SBOREN is ignored)
    BOREN = SBORDIS     BOR enabled in hardware (SBOREN is ignored)

  Brown-out Reset Voltage:
    BORV = 285          BOR set to 2.85V nominal
    BORV = 250          BOR set to 2.5V nominal
    BORV = 220          BOR set to 2.2V nominal
    BORV = 190          BOR set to 1.9V nominal

  Low-Power Brown-out Reset:
    nLPBOR = ON         Low-Power Brown-out Reset enabled
    nLPBOR = OFF        Low-Power Brown-out Reset disabled

  Watchdog Timer Enable bits:
    WDTEN = OFF         WDT disabled in hardware (SWDTEN ignored)
    WDTEN = NOSLP       WDT enabled in hardware, disabled in Sleep mode
                        (SWDTEN ignored)
    WDTEN = SWON        WDT controlled by firmware (SWDTEN enabled)
    WDTEN = ON          WDT enabled in hardware (SWDTEN ignored)

  Watchdog Timer Postscaler:
    WDTPS = 1           1:1
    WDTPS = 2           1:2
    WDTPS = 4           1:4
    WDTPS = 8           1:8
    WDTPS = 16          1:16
    WDTPS = 32          1:32
    WDTPS = 64          1:64
    WDTPS = 128         1:128
    WDTPS = 256         1:256
    WDTPS = 512         1:512
    WDTPS = 1024        1:1024
    WDTPS = 2048        1:2048
    WDTPS = 4096        1:4096
    WDTPS = 8192        1:8192
    WDTPS = 16384       1:16384
    WDTPS = 32768       1:32768

  CCP2 MUX bit:
    CCP2MX = RB3        CCP2 input/output is multiplexed with RB3
    CCP2MX = RC1        CCP2 input/output is multiplexed with RC1

  PORTB A/D Enable bit:
    PBADEN = OFF        PORTB<5:0> pins are configured as digital I/O on Reset
    PBADEN = ON         PORTB<5:0> pins are configured as analog input
                        channels on Reset

  Timer3 Clock Input MUX bit:
    T3CMX = RB5         T3CKI function is on RB5
    T3CMX = RC0         T3CKI function is on RC0

  SDO Output MUX bit:
    SDOMX = RC7         SDO function is on RC7
    SDOMX = RB3         SDO function is on RB3

  Master Clear Reset Pin Enable:
    MCLRE = OFF         RE3 input pin enabled; external MCLR disabled
    MCLRE = ON          MCLR pin enabled; RE3 input disabled

  Stack Full/Underflow Reset:
    STVREN = OFF        Stack full/underflow will not cause Reset
    STVREN = ON         Stack full/underflow will cause Reset

  Single-Supply ICSP Enable bit:
    LVP = OFF           Single-Supply ICSP disabled
    LVP = ON            Single-Supply ICSP enabled if MCLRE is also 1

  Dedicated In-Circuit Debug/Programming Port Enable:
    ICPRT = OFF         ICPORT disabled

  Extended Instruction Set Enable bit:
    XINST = OFF         Instruction set extension and Indexed Addressing mode
                        disabled
    XINST = ON          Instruction set extension and Indexed Addressing mode
                        enabled

  Background Debugger Enable bit:
    DEBUG = ON          Background debugger enabled, RB6 and RB7 are dedicated
                        to In-Circuit Debug
    DEBUG = OFF         Background debugger disabled, RB6 and RB7 configured
                        as general purpose I/O pins

  Block 0 Code Protect:
    CP0 = ON            Block 0 is code-protected
    CP0 = OFF           Block 0 is not code-protected

  Block 1 Code Protect:
    CP1 = ON            Block 1 is code-protected
    CP1 = OFF           Block 1 is not code-protected

  Block 2 Code Protect:
    CP2 = ON            Block 2 is code-protected
    CP2 = OFF           Block 2 is not code-protected

  Block 3 Code Protect:
    CP3 = ON            Block 3 is code-protected
    CP3 = OFF           Block 3 is not code-protected

  Boot Block Code Protect:
    CPB = ON            Boot block is code-protected
    CPB = OFF           Boot block is not code-protected

  Data EEPROM Code Protect:
    CPD = ON            Data EEPROM is code-protected
    CPD = OFF           Data EEPROM is not code-protected

  Block 0 Write Protect:
    WRT0 = ON           Block 0 (0800-1FFFh) is write-protected
    WRT0 = OFF          Block 0 (0800-1FFFh) is not write-protected

  Block 1 Write Protect:
    WRT1 = ON           Block 1 (2000-3FFFh) is write-protected
    WRT1 = OFF          Block 1 (2000-3FFFh) is not write-protected

  Block 2 Write Protect:
    WRT2 = ON           Block 2 (04000-5FFFh) is write-protected
    WRT2 = OFF          Block 2 (04000-5FFFh) is not write-protected

  Block 3 Write Protect:
    WRT3 = ON           Block 3 (06000-7FFFh) is write-protected
    WRT3 = OFF          Block 3 (06000-7FFFh) is not write-protected

  Configuration Registers Write Protect:
    WRTC = ON           Configuration registers (300000-3000FFh) are
                        write-protected
    WRTC = OFF          Configuration registers (300000-3000FFh) are not
                        write-protected

  Boot Block Write Protect:
    WRTB = ON           Boot block (0000-7FFh) is write-protected
    WRTB = OFF          Boot block (0000-7FFh) is not write-protected

  Data EEPROM Write Protect:
    WRTD = ON           Data EEPROM is write-protected
    WRTD = OFF          Data EEPROM is not write-protected

  Block 0 Table Read Protect:
    EBTR0 = ON          Block 0 is protected from table reads executed in
                        other blocks
    EBTR0 = OFF         Block 0 is not protected from table reads executed in
                        other blocks

  Block 1 Table Read Protect:
    EBTR1 = ON          Block 1 is protected from table reads executed in
                        other blocks
    EBTR1 = OFF         Block 1 is not protected from table reads executed in
                        other blocks

  Block 2 Table Read Protect:
    EBTR2 = ON          Block 2 is protected from table reads executed in
                        other blocks
    EBTR2 = OFF         Block 2 is not protected from table reads executed in
                        other blocks

  Block 3 Table Read Protect:
    EBTR3 = ON          Block 3 is protected from table reads executed in
                        other blocks
    EBTR3 = OFF         Block 3 is not protected from table reads executed in
                        other blocks

  Boot Block Table Read Protect:
    EBTRB = ON          Boot block is protected from table reads executed in
                        other blocks
    EBTRB = OFF         Boot block is not protected from table reads executed
                        in other blocks

 In this case, i want to use internal oscillator (not need external oscillator is the advantage of this microcontroller in front of 18LF2550) at higher available speed, 48MHz, so looking at the datasheet (attached at the end of this post) my configuration bits are:


  #pragma config FOSC=INTOSCIO
  #pragma config PLLSEL=PLL3X,CFGPLLEN=OFF,CPUDIV=NOCLKDIV,LS48MHZ=SYS48X8
  #pragma config IESO=ON,FCMEN=ON,PCLKEN=ON,BOREN=OFF
  #pragma config nPWRTEN=OFF,nLPBOR=OFF,BORV=220,WDTPS=32768,WDTEN=OFF
  #pragma config MCLRE=OFF,SDOMX=RC7,T3CMX=RC0,DEBUG=OFF,STVREN=ON
  #pragma config ICPRT=OFF,XINST=OFF,LVP=OFF,CP0=OFF,CP1=OFF,CP2=OFF
  #pragma config CP3=OFF,CPD=OFF,CPB=OFF,WRT0=OFF,WRT1=OFF,WRT2=OFF
  #pragma config WRT3=OFF,WRTB=OFF,WRTC=OFF,WRTD=OFF,EBTR0=OFF,EBTR1=OFF
  #pragma config EBTR2=OFF,EBTR3=OFF,EBTRB=OFF

 These configuration bits means:

  • Internal oscillator
  • PLL multiplier x3, PLL disabled, no clock division, USB divider on 8 (working at 48 MHz)
  • Oscillator switchover, Clock monitor, No brown out reset
  • Power up timer disabled, Reset on Low Power disabled, brown out on 2.2V, Watchdog division to 32768, Watchdog disabled
  • Master clear off, SDO on RC7, Timer3 input on RC0, Debug off, Stack over/underflow reset enabled
  • Icport disabled (must be in this way), No extended instruction set, No low power voltage
  • Disabled all memories protection

Maybe you noticed the PLL is disabled when we just use it to set frecuency up from 16MHz (internal oscillator) to 48MHz multiplying by x3. I make this task direcly on source code (i tried in another way and didn't work). So first code executed in main method is:


  OSCTUNE = 0x80; //3X PLL ratio mode selected (same as config bit)
  OSCCON = 0x70;  //Switch to 16MHz HFINTOSC
  OSCCON2 = 0x10; //Enable PLL, SOSC, PRI OSC drivers turned off

 
Using this configuration, we can continue. Next step will be to program a bootloader into it to be able to program without any external tool.

Starting with PIC18LF25K50 << | >> MPLAB C18 v3.46 for MAC OS X

AttachmentSize
18LF25K50_Datasheet.pdf8.66 MB